ElasticSimMATE: a Fast and Accurate gem5 Trace-Driven Simulator for Multicore Systems

International audienceMulticore system analysis requires efficient solutions for architectural parameter and scalability exploration. Long simulation time is the main drawback of current simulation approaches. In order to reduce the simulation time while keeping the accuracy levels, trace-driven simulation approaches have been developed. However, existing approaches do not allow multicore exploration or do not capture the behavior of multi-threaded programs. Based on the gem5 simulator, we developed a novel synchronization mechanism for multicore analysis based on the trace collection of synchronization events, instruction and dependencies. It allows efficient architectural parameter and scalability exploration with acceptable simulation speed and accuracy

Instalación, administración y control de servicios de infraestructura it bajo el Sistema Operativo Zentyal Server 5.0

En el siguiente documento se evidenciará la instalación del sistema operativo Zentyal server en una máquina virtual basada en virtualbox para así poder administrar y controlar los servicios de infraestructura IT como son: DHCP Server, DNS Server y Controlador de Dominio, Proxy no transparente, Cortafuegos, File Server y Print Server y VPN. Además, el Zentyal server cuenta con una interfaz gráfica que es operativa desde la web lo que permite configurar sus servicios de acuerdo a las necesidades o requerimientos que se tengan en cualquier proyecto establecido.The following document will demonstrate the installation of the Zentyal server operating system in a virtualbox-based virtual machine in order to manage and control IT infrastructure services such as: DHCP Server, DNS Server and Domain Controller, Non-transparent proxy, Firewall, File Server and Print Server and VPN

Technique hybride d'estimation de puissance pour l’amélioration des modèles de puissance haut-niveau

Une forte consommation d'énergie est un facteur clé impactant les performances des systèmes sur puce (SoC). Des modèles de puissance précis et efficaces doivent être introduits le plus tôt possible dans le flot de conception lorsque la majeure partie du potentiel d'optimisation est possible. Cependant, l'obtention d’une estimation précise ne peut être assurée en raison du manque de connaissance détaillées de la structure du circuit final. La conception actuelle de SoC repose sur la réutilisation de cœur IP (Intelectual Property) car des informations de bas niveau sur les composants du circuit ainsi que la structure sont disponibles. Ainsi, la précision de l'estimation au niveau du système peut être amélioré en utilisant ces informations et en élaborant une méthode d'estimation qui correspond aux besoins de modélisation de puissance des cœurs IP.La principale contribution de cette thèse est le développement d’une technique d'estimation hybride (HPET), dans laquelle les informations provenant de différents niveaux d'abstraction sont utilisées pour évaluer la consommation d'énergie de manière rapide et précise. HPET est basé sur une méthodologie efficace de caractérisation de la bibliothèque technologique et une approche hybride de modélisation de puissance. Les résultats des simulations obtenues avec HPET ont été validés sur différents circuits de référence synthétisés en utilisant la technologie 28nm "Fully Depleted Silicon On Insulator" (FDSOI). Les résultats expérimentaux montrent que nous pouvons atteindre en moyenne jusqu'à 70X d'amélioration en vitesse de calcul tout en ayant une précision au niveau transistor. Pour les deux types puissance analysés (instantanée et moyenne), les résultats de HPET sont bien corrélés par rapport à ceux calculés avec SPECTRE et Primetime-PX. Cela démontre que HPET est une technique efficace pour améliorer la création de macro-modèles de puissance à haut niveau d'abstraction.High power consumption is a key factor hindering System-on-Chip (SoC) performance. Accurate and efficient power models have to be introduced early in the design flow when most of the optimization potential is possible. However, early accuracy cannot be ensured because of the lack of precise knowledge of the final circuit structure. Current SoC design paradigm relies on IP (Intellectual Property) core reuse since low-level information about circuit components and structure is available. Thus, power estimation accuracy at the system level can be improved by using this information and developing an estimation methodology that fits IP cores power modeling needs.The main contribution of this thesis is the development of a Hybrid Power Estimation Technique (HPET), in which, information coming from different abstraction levels is used to assess the power consumption in a fast and accurate manner. HPET is based on an effective characterization methodology of the technology library and an efficient hybrid power modeling approach. Experimental results, derived using HPET, have been validated on different benchmark circuits synthesized using the 28nm “Fully Depleted Silicon On Insulator” (FDSOI) technology. Experimental results show that in average we can achieve up to 70X speedup while having transistor-level accuracy. For both analyzed power types (instantaneous and average), HPET results are well correlated with respect to the ones computed in SPECTRE and Primetime-PX. This demonstrates that HPET is an effective technique to enhance power macro-modeling creation at high abstraction levels

Trace-driven simulation of multithreaded applications in gem5

International audienc

Trace-driven simulation of multithreaded applications in gem5

International audienc

A gem5 trace-driven simulator for fast architecture exploration of OpenMP workloads

International audienceArchitecture parameter exploration is one of the main analysis that needs to be performed in order to ensure that a multicore system has an optimal set of parameters. The main drawback of current simulation approaches is the long simulation times in order to extract performance metrics while varying a system parameter. Trace-driven simulation approaches allow to abstract selected components of the system under analysis by creating traces during the execution time of an application. This technique reduces the simulation time while keeping the accuracy levels. Even tough trace-driven techniques have proven to be useful, most of them are focused on mono-core systems, and some do not completely capture the behavior of multi-threaded programs. In this regard, we developed a trace-driven simulation approach based on the gem5 framework. This approach is based on a collection phase of the instructions and dependencies of a given application and two extra traces depending on the selected analysis. It allows weak and strong scaling analysis along with the possibility to perform extensive parameter exploration analysis. For weak scaling analysis simulations, we collect synchronization traces for OpenMP applications, and for strong scaling analysis, we collect task traces for OmpSs applications

A Hybrid Power Estimation Technique to improve IP power models quality

International audienceNowadays, power consumption is the one key factor that hinders System-on-Chip (SoC) performance. In order to reduce the power consumption, accurate and efficient power models have to be introduced early in the design flow, when most of the optimization potential is obtained. However, early accuracy cannot be ensured because of the lack of precise knowledge of the circuit structure. Current SoC design paradigm relies on Intellectual Property (IP) reuse, and low-level information about circuit components and structure is usually available. Thus, if we use this information and develop an estimation methodology that fits IP power modeling needs, the estimation accuracy at system level will be improved. This paper presents a Hybrid Power Estimation Technique (HPET). It is based on an effective library characterization methodology and an efficient hybrid power modeling approach to accurately and quickly assess gate-level power consumption. The aim is to give valuable and accurate physical information to design teams so they can ensure that the correct optimization techniques are implemented. Our approach can be used to compute both realistic instantaneous power and average power on a single simulation time. We performed experiments on different benchmark circuits synthesized using the 28nm FDSOI technology. To validate the proposed technique, we correlated our results with SPECTRE and PrimeTime-PX simulations. Our results showed that we can achieve up to 144× speedup on the simulation runtime with a mean error of about 6% and 13% for the instantaneous and average power components respectively

HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization

International audienceHigh power consumption is a key factor hindering system-on-chip (SoC) performance. Accurate and efficient power models have to be introduced early in the design flow when most of the optimization potential is possible. However, early accuracy cannot be ensured because of the lack of precise knowledge of the final circuit structure. Current SoC design paradigm relies on intellectual property (IP) core reuse since low-level information about circuit components and structure is available. Thus, power estimation accuracy at the system level can be improved by using this information and developing an estimation methodology that fits IP cores power modeling needs. The main contribution of this paper is the development and validation of a hybrid power estimation technique (HPET), in which information coming from different abstraction levels is used to assess the power consumption in a fast and accurate manner. HPET is based on an effective characterization methodology of the technology library and an efficient hybrid power modeling approach. Experimental results, derived using HPET, have been validated on different benchmark circuits synthesized using the 28nm “fully depleted silicon on insulator” (FDSOI) technology. Experimental results show that in average we can achieve up to 68× improvement in power estimation run-time while having transistor-level accuracy. For both analyzed power types (instantaneous and average), HPET results are well correlated with respect to the ones computed in SPECTRE and Primetime-PX. This demonstrates that HPET is an effective technique to enhance power macro-modeling creation at high abstraction levels

A hybrid power modeling approach to enhance high-level power models

International audiencePower management techniques are applied at high abstraction levels to reduce chip power consumption. Accurate and efficient power models are needed as early as possible in the design flow to ensure that correct saving decisions are taken. However, accuracy at those levels cannot be ensured, as there is not exact knowledge of the circuit structure. Then, power models based on estimation techniques at lower abstraction levels are desired. In this work, we propose a hybrid power modeling approach based on an effective library characterization methodology and an efficient power estimation flow to accurately assess gate-level power consumption. The main idea is to enhance the high-level power models by providing realistic information of the physical design. We perform experiments on ISCAS'85 benchmark circuits synthesized with a 28nm FDSOI technology. To prove the validity of our approach, we compare our results with SPECTRE simulations and show that we can achieve a 144X speedup on the runtime with a transistor-like accuracy